Title :
Explorer: a trade-off analysis tool for architecture synthesis
Author :
Nagasamy, Vijay ; Dangelo, Carlos
Author_Institution :
LSI Logic Corp., Milpitas, CA, USA
Abstract :
A tool is described for performing automated partitioning and high-level `what-if´ analysis during the early stages of digital hardware synthesis. The tool accepts behavioral descriptions in VHDL (VHSIC hardware description language) as input and assists the designer in exploring design space at the architectural level. The tool supports a top-down design methodology while making use of bottom-up design information such as area and delay of modules, estimates for interconnect and routing. Use of such estimates helps the designer in quickly evaluating alternative architectures before implementing a design. The tool is written in Prolog and makes use of knowledge of the target technology and provides a very flexible environment for design trade-off analysis
Keywords :
circuit CAD; digital integrated circuits; digital systems; logic CAD; Explorer; Prolog; VHDL; VHSIC hardware description language; architectural level; architecture synthesis; behavioral descriptions; bottom-up design information; design trade-off analysis; digital hardware synthesis; top-down design methodology; trade-off analysis tool; Circuit synthesis; Delay estimation; Design methodology; Hardware; Large scale integration; Logic; Parameter estimation; Performance analysis; Routing; Space exploration;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257405
