Explorer: a trade-off analysis tool for architecture synthesis

A tool is described for performing automated partitioning and high-level `what-if´ analysis during the early stages of digital hardware synthesis. The tool accepts behavioral descriptions in VHDL (VHSIC hardware description language) as input and assists the designer in exploring design space at the architectural level. The tool supports a top-down design methodology while making use of bottom-up design information such as area and delay of modules, estimates for interconnect and routing. Use of such estimates helps the designer in quickly evaluating alternative architectures before implementing a design. The tool is written in Prolog and makes use of knowledge of the target technology and provides a very flexible environment for design trade-off analysis