DocumentCode :
3439777
Title :
RISC architecture trends
Author :
Bhandarkar, Dileep
Author_Institution :
Digital Equipment Corp., Maynard, MA, USA
fYear :
1991
fDate :
13-16 May 1991
Firstpage :
345
Lastpage :
352
Abstract :
RISC (reduced instruction set computer) architecture is now widely accepted as a means for achieving high performance with microprocessor technology. The first generation of RISC systems offers almost three times higher performance than their CISC (complex instruction set computer) counterparts using similar technology and machine organization. Continuing advances in semiconductor technology allow superscalar and superpipelined implementations of RISC architectures. Such implementation can provide a tremendous improvement in performance. The next generation RISC machines will feature superscalar or superpipelined single chip implementation with on-chip caches
Keywords :
reduced instruction set computing; RISC architecture trends; microprocessor technology; on-chip caches; reduced instruction set computer; superpipelined; superscalar; Application software; Computer architecture; Delay; Microprocessors; Parallel processing; Pipelines; Proposals; Reduced instruction set computing; Technological innovation; USA Councils;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
Type :
conf
DOI :
10.1109/CMPEUR.1991.257408
Filename :
257408
Link To Document :
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