Title :
An efficient hardwired router for a 3D-mesh interconnection network
Author :
Béchennec, J.L. ; Germain, C. ; Neri, V.
Author_Institution :
LRI-Comput. Archit. & VLSI Design, Orsay, France
Abstract :
A routing circuit for massively parallel message-passing architectures is presented. This circuit meets the area requirements of a monochip processing element and is time-efficient. It implements a new routing algorithm, forced routing. It is shown that the forced routing algorithm may be hardwired in less than a 10 mm2 circuit in a CMOS 1.2 μm process. Several design choices are discussed and tested for the arbiter, which is the most critical part of the circuit
Keywords :
CMOS integrated circuits; multiprocessor interconnection networks; 1.2 micron; 10 mm; 3D-mesh interconnection network; CMOS; arbiter; forced routing; hardwired router; massively parallel message-passing architectures; monochip processing element; routing circuit; time-efficient; CMOS process; CMOS technology; Circuit testing; Computer architecture; Multiprocessor interconnection networks; Packaging machines; Parallel architectures; Random access memory; Routing; Very large scale integration;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257409
