Title :
A testable PLA design with low overhead and ease of test generation
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to further utilize the `don´t care´ assignment by introducing the control of both true and complement bits of some inputs to meet the requirement of distance-2 test sets. This approach is applied to the BARNEW PLA, and results support the claim that the hardware overhead of this technique is negligible and the ease of test generation is preserved
Keywords :
logic CAD; logic arrays; logic testing; BARNEW; design-for-testability technique; distance-2 test sets; ease of test generation; testable PLA design; Circuit faults; Circuit testing; Design for testability; Design methodology; Hardware; Logic design; MOSFETs; Programmable logic arrays; Switches; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25741
