A signalling system for multiprocessors

The main functions and the architecture for a general-purpose signaling subsystem (for a shared memory, common bus multiprocessor) suitable for a VLSI implementation are presented. The performance of the subsystem for different load conditions has been evaluated by means of simulations. Simulation results show that, according to the steady-state analysis, the bus usage remains low at all clock frequencies except 1 MHz. Other results show that the number of collisions is less than 5% for speeds of 5 and 10 MHz, and less than 20% for 2 MHz. The average delay in dispatching an interrupt request is around 20 μs at 2 MHz, but becomes around 5 μs at 10 MHz (of which 4.1 μs are necessary to transmit the interrupt message)