HARP: a VLIW RISC processor

HARP, (the Hatfield RISC processor), is a reduced instruction set processor. The major aim of the HARP project is to develop a VLIW (very long instruction word) RISC (reduced instruction set computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC-type instructions. Investigations to date support the hypothesis that this goal can be achieved by the development of an integrated processor-compiler pair designed to support low-level parallelism identified by the compiler. A description is presented of the HARP architecture and those hardware features which will support parallel instruction execution. Parallelism is provided in the hardware by multiple instruction pipelines which execute independent RISC-like instructions simultaneously. The principal techniques used to exploit the available parallelism are efficient pipelining, register bypassing, optional register writeback, and conditional execution of instructions