Non Inverting Differential Asymmetrical CMOS Comparator with Intrinsic Hysteresis and Adjustable Asymmetry

Author

lonescu, R. ; Mita, O. ; Vladoianu, F. ; Brezeanu, G.

Author_Institution

Politeh. Univ. of Bucharest, Bucharest

Volume

2

fYear

2007

fDate

Oct. 15 2007-Sept. 17 2007

Firstpage

555

Lastpage

558

Abstract

A non inverting differential asymmetrical CMOS comparator with intrinsic hysteresis and adjustable asymmetry is presented in this paper. A widely tunable hysteresis window was obtained. The threshold voltage of the comparator is adjustable up to +150 mV of the input differential signal in 16 steps. The input differential signal is 400 mVpp with a frequency of 1 MHz. The bias current is 50 uA and the supply voltage is 3.3 V. The design was made in basic gpdk Cadence integrated circuits front to back 0.18 um CMOS technology. The response time was minimized and also the difference between the phases of the outputs was minimized. This comparator can be used, with good performance, in signal conditioning chains.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); Cadence integrated circuits; adjustable asymmetry; frequency 1 MHz; input differential signal; intrinsic hysteresis; noninverting differential asymmetrical CMOS comparator; signal conditioning chains; threshold voltage; voltage 3.3 V; CMOS logic circuits; CMOS technology; Delay; Frequency; Hysteresis; Integrated circuit technology; Inverters; Signal processing; Threshold voltage; Tunable circuits and devices; CMOS comparator; hysteresis; signal conditioning;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2007. CAS 2007. International

Conference_Location

Sinaia

ISSN

1545-827X

Print_ISBN

978-1-4244-0847-4

Type

conf

DOI

10.1109/SMICND.2007.4519784

Filename

4519784