Dedicated systolic VLSI circuit as adaptive filter for acoustic echo canceller

The design of a single-chip adaptive filter to be used in an echo canceller board is reported. The filter is designed by using bit-level systolic macrocells as building blocks of the architecture. The filter consists of a high-speed systolic core, characterized by a high clock frequency, an easy and regular design, and a low-speed interface circuit. Peculiar characteristics are the high number of taps (1024) and the 16×16 systolic multiplier macrocell. The techniques adopted in the reduction of the occupied area are also described