Dedicated systolic VLSI circuit as adaptive filter for acoustic echo canceller

Author

Roncella, R. ; Saletti, R. ; Terreni, P.

Author_Institution

Istituo di Elettronica e Teleccomunicazioni, Pisa Univ., Italy

fYear

1991

fDate

13-16 May 1991

Firstpage

393

Lastpage

397

Abstract

The design of a single-chip adaptive filter to be used in an echo canceller board is reported. The filter is designed by using bit-level systolic macrocells as building blocks of the architecture. The filter consists of a high-speed systolic core, characterized by a high clock frequency, an easy and regular design, and a low-speed interface circuit. Peculiar characteristics are the high number of taps (1024) and the 16×16 systolic multiplier macrocell. The techniques adopted in the reduction of the occupied area are also described

Keywords

VLSI; acoustic signal processing; adaptive filters; digital signal processing chips; echo; echo suppression; multiplying circuits; systolic arrays; acoustic echo canceller; bit-level systolic macrocells; echo canceller board; high clock frequency; high-speed systolic core; low-speed interface circuit; single-chip adaptive filter; systolic VLSI circuit; systolic multiplier macrocell; Adaptive filters; Algorithm design and analysis; Application software; Application specific integrated circuits; Clocks; Digital signal processors; Echo cancellers; Signal processing algorithms; VHF circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257417

Filename

257417