Title :
HTPG: hybrid test pattern generation for reducing test storage
Author :
Kalyanam, Vijay Kiran ; Touba, Nur A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX
Abstract :
This paper describes a hybrid test pattern generation (HTPG) scheme that is a hybrid approach between BIST and conventional external testing. HTPG speeds up conventional ATPG and also reduces tester storage compared to full external testing. Experimental results show a comparison between the proposed HTPG scheme with conventional ATPG and BIST and also the effectiveness of different percentages of pseudo-random and deterministic data in a test pattern generated by HTPG. The results show that having 10-15% deterministic data per scan vector is most effective
Keywords :
automatic test pattern generation; built-in self test; ATPG; HTPG; automatic test pattern generation; built-in self-test; deterministic data; hybrid test pattern generation; pseudo-random data; test storage reduction; Automatic test pattern generation; Automatic testing; Bandwidth; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Moore´s Law; Semiconductor device testing; Test pattern generators;
Conference_Titel :
Autotestcon, 2005. IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-9101-2
DOI :
10.1109/AUTEST.2005.1609232
