General purpose neuroemulator architecture: design and VHDL simulation

Author

Medrano-Marqucs, N. ; Martín-Del-Brío, Bonifacio

Author_Institution

Dept. de Ingenieria Electron. y Comunicaciones, Zaragoza Univ., Spain

Volume

3

fYear

1998

fDate

1998

Firstpage

293

Abstract

A new SIMD architecture for artificial neural network emulation, based on bus segmentation, is proposed. As demonstration, we implement on this architecture the well known multilayer perceptron with backpropagation learning. VHDL simulations are carried out, being compared to simulations on a general purpose computer. System scalability (performance in relation to the number of processing units included) is analysed. This architecture is being now implemented by means of FPGA devices; results for an arithmetic unit are already provided

Keywords

backpropagation; field programmable gate arrays; hardware description languages; logic CAD; multilayer perceptrons; neural net architecture; parallel architectures; FPGA device; SIMD architecture; System scalability; VHDL simulation; arithmetic unit; artificial neural network emulation; backpropagation learning; general purpose computer; multilayer perceptron; neuroemulator architecture; Artificial neural networks; Backpropagation; Computational modeling; Computer architecture; Computer simulation; Emulation; Field programmable gate arrays; Multilayer perceptrons; Performance analysis; Scalability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813991

Filename

813991