Modeling the electrical behavior of an EPLD cell array, in the presence of lithography induced spot defects

Author

Corsi, F. ; De Venuto, D. ; Martino, S. ; Morandi, C.

Author_Institution

Dipartimento di Elettrotecnica ed Elettronica, Bari Univ., Italy

fYear

1991

fDate

13-16 May 1991

Firstpage

521

Lastpage

525

Abstract

The inductive fault analysis approach has been used to study the circuit behavior of the regular array of an electrical programmable logic device. The analysis is based on the knowledge of the chip layout and fabrication technology and takes into account only single localized defects related to the photolithographic process. A list of physical changes in the cell layout has been derived and interpreted at circuit level. Functional faults have been distinguished from parametric degradations and the validity of the stuck-at and cross-point fault models has been assessed

Keywords

circuit layout CAD; failure analysis; logic arrays; logic testing; photolithography; EPLD cell array; cell layout; chip layout; circuit behavior; cross-point fault models; electrical behavior; electrical programmable logic device; fabrication technology; functional faults; inductive fault analysis; lithography induced spot defects; localized defects; parametric degradations; photolithographic process; physical changes; regular array; stuck at fault models; Bidirectional control; Circuit faults; EPROM; Flip-flops; Insulation; Lithography; Macrocell networks; Pins; Scanning electron microscopy; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257441

Filename

257441