45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

Author

Okuno, M. ; Okabe, K. ; Sakuma, T. ; Suzuki, K. ; Miyashita, T. ; Yao, T. ; Morioka, H. ; Terahara, M. ; Kojima, Y. ; Watatani, H. ; Sugimoto, K. ; Watanabe, T. ; Hayami, Y. ; Mori, T. ; Kubo, T. ; Iba, Y. ; Sugiura, I. ; Fukutome, H. ; Morisaki, Y. ; Min

Author_Institution

Fujitsu Labs. Ltd., Fujitsu Ltd., Kuwana

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

52

Lastpage

55

Abstract

We describe the integration of a 45-nm node CMOS for low operation power (LOP) application. The SD extension profile along with a strain channel and a thin-gate-SiON were optimized to keep high drive current at the 45-nm node. A novel STI structure was developed to reduce the SRAM cell size. Nano-clustering silica (NCS) without a middle-etch stopper (MES) was also developed to decrease the wire capacitance. As a result, we achieved an excellent LOP device operation with conventional processing, and we produced a 50% smaller SRAM cell-size as compared to the 65-nm node

Keywords

CMOS integrated circuits; SRAM chips; low-power electronics; silicon compounds; 45 nm; 65 nm; CMOS integration; SRAM cell size; SiON; middle-etch stopper; nanoclustering silica; strain channel; wire capacitance; Capacitance; Capacitive sensors; Costs; Delay; MOS devices; Nitrogen; Random access memory; Silicon compounds; Silicon on insulator technology; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609264

Filename

1609264