A loop-based built in self test strategy for ASIC design

Author

Findlay, P.A. ; Johnson, B.A.

Author_Institution

Electron. Res. & Dev. Centre, Hatfield Polytech, UK

fYear

1991

fDate

13-16 May 1991

Firstpage

575

Lastpage

579

Abstract

A method is described for including built-in self-test (BIST) in digital application-specific integrated circuits (ASICs). All the general logic (i.e., nonmemory parts) of an ASIC is tested as a single partition of interconnected self-test loops. The loops are based on simple, regular test structures and perform simultaneous test pattern generation and response compaction. The occurrence of fault masking due to local register interdependence is minimized by using special shift-register macros. The BIST method has been successfully implemented in a 17K gate-equivalent ASIC, for which a general logic fault coverage of 92% is achieved after only 166 test cycles

Keywords

application specific integrated circuits; built-in self test; integrated circuit testing; logic CAD; logic testing; macros; shift registers; ASIC design; digital application-specific integrated circuits; fault coverage; fault masking; general logic; interconnected self-test loops; local register interdependence; loop-based built in self test strategy; response compaction; shift-register macros; test pattern generation; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Integrated circuit interconnections; Logic testing; Performance evaluation; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257452

Filename

257452