A methodology for the control and custom VLSI implementation of large-scale Clos networks

A control algorithm is developed and implemented for a three-stage Clos network which results in using a multiple-chip approach. The system will be nonblocking in the strict sense and completely self-routing, i.e. the controller for the network will reside in the network and not in a separate computer that runs a program that controls switches to the interconnect array. Intermodule communication required for network operation is described followed by a discussion of how the number of network inputs/outputs may be varied. A delay model of the network is developed