3441077

A low power parallel architecture variable order b-spline interpolator for fractional sampling rate conversion

Mondal, Sabyasachi ; De, Arijit

Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., West Bengal, India

2004

11-14 Dec. 2004

555

559

interpolation; low-power electronics; parallel architectures; power consumption; roundoff errors; signal generators; signal processing; signal processing equipment; splines (mathematics); statistical analysis; 16-bit fixed point parallel architecture; B-Spline basis generator; B-Spline interpolation techniques; finite word length effect; low power design technique; power consumption; sampling rate conversion system; statistical measure; Circuits; Design engineering; Energy consumption; Hardware; Parallel architectures; Parallel processing; Sampling methods; Signal processing algorithms; Signal sampling; Spline;

English

ieee

Signal Processing and Communications, 2004. SPCOM '04. 2004 International Conference on

0-7803-8674-4

conf

10.1109/SPCOM.2004.1458521

1458521