Set-associative dynamic random access memory

Static-column dynamic RAMs (random-access memories) offer fast access to successive locations within a single row, a fact which has been used in their implementation in fast cacheless memory systems. Such caches are necessarily nonassociative (direct-mapped), limiting their performance relative to set-associative caches of similar total capacity. The authors describe an architecture for dynamic RAM chips which circumvents this limitation by providing several alternative static row buffers on each chip. Cacheless memory systems utilizing these devices are able to achieve the performance characteristics of relatively expensive set-associative cached memories using only economical high-density RAM parts. Simulation results on set-associate dynamic RAMs (SADRAMs) are presented and some plausible roles for SADRAMs in various architectural contexts are noted