Title :
Switch level test pattern production for CMOS ICs
Author :
Flottes, Marie-Lise ; Landrault, Christian ; Pravossoudovitch, S.
Author_Institution :
Lab. d´´Autom. et de Microelectron., Montpellier II Univ., France
Abstract :
An overview is presented of the different possibilities which allow the implementation of switch-level test pattern production for CMOS macrocells. A discussion is presented of fault modeling, fault list generation, circuit modeling and fault equivalence. Switch-level fault simulation is outlined along with switch-level ATPG (automatic test pattern generation)
Keywords :
CMOS integrated circuits; automatic testing; circuit analysis computing; failure analysis; integrated circuit testing; CMOS macrocells; automatic test pattern generation; circuit modeling; fault equivalence; fault list generation; fault modeling; fault simulation; switch-level test pattern production; Automatic control; Circuit faults; Circuit testing; Macrocell networks; Production; Programmable logic arrays; Semiconductor device modeling; Sequential analysis; Switches; Very large scale integration;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257470
