Title :
Design of online reconfigurable array processors
Author_Institution :
Inst. fur Theor. Nachrichtentech. und Informationsverarbeitung, Hannover Univ., Germany
Abstract :
A design procedure for nonredundant arrays of processing elements, which is applicable to a wide class of algorithms, is extended for the design of online reconfigurable arrays. Online reconfiguration means it is performed concurrently with calculation. It is started at runtime by faults detected at run time. This requires the use of self-checking processing elements (PEs). After a brief introduction to the systematic design of array processors, the basics of the extension to the design of online reconfigurable array processors are discussed
Keywords :
VLSI; cellular arrays; digital signal processing chips; fault tolerant computing; multiprocessor interconnection networks; parallel architectures; nonredundant arrays; online reconfigurable array processors; run time faults detection; self-checking processing elements; Algorithm design and analysis; Circuit faults; Digital signal processing; Digital signal processing chips; Fault tolerance; Process design; Processor scheduling; Signal design; Signal processing algorithms; Very large scale integration;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257477
