A hardware/software concurrent design for a real-time SP@ML MPEG2 video-encoder chip set

Author

Ikeda, Makoto ; Okubo, Takanori ; Abe, Takashi ; Ito, Yu ; Tashiro, Yoichiro ; Kasai, Ryouhei

Author_Institution

NTT LSI Labs., Atsugi

fYear

1996

fDate

11-14 Mar 1996

Firstpage

320

Lastpage

326

Abstract

This paper presents a design for a real-time MPEG2 SP@ML video-encoder chip set. Its main features are: hardware/software partitioning based on a software encoder analysis, and a pipeline architecture where hardware and software interact closely and smoothly. We use a hardware/software concurrent design technique with fast verification to avoid major modifications at architectural and RTL levels. The chips were successfully fabricated with 0.5-μm CMOS technology

Keywords

CMOS digital integrated circuits; digital signal processing chips; integrated circuit design; pipeline processing; video coding; 0.5 mum; CMOS technology; fast verification; hardware/software concurrent design; hardware/software partitioning; pipeline architecture; real-time MPEG2 SP@ML video-encoder chip; software encoder analysis; CMOS technology; Computer architecture; Design methodology; Encoding; Hardware; Laboratories; Large scale integration; Pipelines; Software design; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494320

Filename

494320

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3441333