Constructive analysis of cyclic circuits

Author

Shiple, Thomas R. ; Berry, Gérard ; Touati, Hemé

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1996

fDate

11-14 Mar 1996

Firstpage

328

Lastpage

333

Abstract

Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard synchronous behavior, and if so, produces an equivalent circuit without combinational loops. We present applications to hardware and software synthesis from the Esterel synchronous programming language

Keywords

equivalent circuits; hardware description languages; iterative methods; logic CAD; program compilers; sequential circuits; Esterel synchronous programming language; behavioral compiling; circuit size; combinational loops; cyclic circuits; equivalent circuit; high-level language; sequential circuit; symbolic algorithm; synchronous circuit design; Boolean functions; Circuit analysis; Circuit synthesis; Combinational circuits; Computer languages; Delay; Equations; Hardware; High level languages; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494321

Filename

494321