A 42-Gb/s Decision Circuit in 0.13µm CMOS

Author

Liang, Bangli ; Kwasniewski, Tad ; Chen, Dianyong

Author_Institution

Carleton Univ., Ottawa, ON

fYear

2008

fDate

5-8 May 2008

Firstpage

339

Lastpage

342

Abstract

In this paper, a decision circuit based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. This decision circuit achieved by master-slave flip-flops (MS-FFs) with opposite clock can operate at a bit rate of 40-Gb/s and beyond. Current-mode logic (CML) is adopted due to the higher speed compared to static CMOS and the robustness against common-mode disturbances. A 3-stage output buffer is employed to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The decision circuit uses a single 1.2V supply and consumes a total current of 33mA. And the chip area is only 0.63mm2 with bonding pads.

Keywords

CMOS integrated circuits; current-mode logic; decision circuits; flip-flops; optical communication; 3-stage output buffer; CMOS; bit rate 40 Gbit/s; bit rate 42 Gbit/s; current 33 mA; current-mode logic; decision circuit; master-slave flip-flop; on-chip shunt peaking inductor; optical communication system; size 0.13 mum; split-resistor load; voltage 1.2 V; Bit rate; CMOS logic circuits; Clocks; Flip-flops; Master-slave; Optical buffering; Optical design; Optical fiber communication; Robustness; Shunt (electrical); CMOS CML; Optical communication; Shunt peaking; Split-resistor;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Networks and Services Research Conference, 2008. CNSR 2008. 6th Annual

Conference_Location

Halifax, NS

Print_ISBN

978-0-7695-3135-9

Type

conf

DOI

10.1109/CNSR.2008.15

Filename

4519878