Title :
Novel dielectric slots in Cu interconnects for suppressing stress-induced void failure
Author :
Lim, Y.K. ; Pey, K.L. ; Tan, J.B. ; Lee, T.J. ; Vigar, D. ; Hsia, L.C. ; Lim, Y.H. ; Kamat, N.R.
Author_Institution :
Chartered Semicond. Manuf. Ltd., Singapore
Abstract :
Novel dielectric slots were incorporated into advanced Cu interconnects using a damascene process without additional masking steps. The dielectric slots were found to be effective in suppressing stress-induced void failure. Together with physical analysis results, the possible mechanisms that improve the stress migration reliability of advanced Cu interconnects are discussed
Keywords :
copper; dielectric materials; integrated circuit interconnections; integrated circuit reliability; Cu interconnects; damascene process; dielectric slots; masking steps; physical analysis; stress induced void failure; stress migration reliability; Dielectrics; Integrated circuit interconnections; Integrated circuit technology; Lead; Manufacturing processes; Microelectronics; Pulp manufacturing; Temperature; Tensile stress; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609300
