Comprehensive fault modeling and simulation in CMOS ICs

A brief overview is presented of fault modeling and simulation in CMOS circuits, with particular regard to cases not adequately represented in terms of the classical fault model. The most important models used to describe transistor faults, bridgings and delay faults are presented, and the main problems to be solved for their implementation in circuit simulators are discussed in some detail. Typical coverage results of these fault types obtained with stuck-at-oriented test sequences are also presented in order to show the need to explicitly consider non-stuck-at faults when evaluating the quality of test sequences