Title :
XPRESS: a cell layout generator with integrated transistor folding
Author :
Gupta, Avaneendra ; The, Siang-Chun ; Hayes, John P.
Author_Institution :
Div. of Design Technol., Intel Corp., Santa Clara, CA, USA
Abstract :
We describe a method for generating area-efficient layouts of complex CMOS cells in the one-dimensional (linear) style. Its key features are the support for unrestricted circuit structures, transistor sizing via a novel folding technique that integrates folding into the synthesis algorithms, and optimal diffusion sharing. The method has been implemented in the XPRESS cell syntheses tool at the Intel Corporation, where it is in active use to lay out datapath cells for microprocessors
Keywords :
CMOS digital integrated circuits; CMOS integrated circuits; circuit layout CAD; integrated circuit layout; Intel Corporation; XPRESS; area-efficient layouts; cell layout generator; cell syntheses tool; complex CMOS cells; datapath cells; integrated transistor folding; linear style; one-dimensional style; optimal diffusion sharing; synthesis algorithms; transistor sizing; CMOS logic circuits; CMOS technology; Circuit synthesis; Computer science; Ear; Educational institutions; Libraries; Minimization; Network synthesis; Productivity;
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7424-5
DOI :
10.1109/EDTC.1996.494331
