DocumentCode
3441617
Title
A high speed error correcting converter for residue number processing
Author
Zhang, C.N. ; Cheng, H.D.
Author_Institution
Dept. of Comput. Sci., Regina Univ., Sask., Canada
fYear
1991
fDate
13-16 May 1991
Firstpage
816
Lastpage
820
Abstract
A novel pipelined systolic design for residue error correction using the Chinese remainder theorem (CRT) is described. This design has a higher throughput compared to previous methods and minimum time latency. The design also has overflow detection and self-diagnosing abilities
Keywords
digital arithmetic; error correction; pipeline processing; systolic arrays; Chinese remainder theorem; error correcting converter; minimum time latency; overflow detection; pipelined systolic design; residue error correction; residue number processing; self-diagnosing; Arithmetic; Cathode ray tubes; Clocks; Concurrent computing; Delay; Error correction; Fault detection; Hardware; Signal design; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location
Bologna
Print_ISBN
0-8186-2141-9
Type
conf
DOI
10.1109/CMPEUR.1991.257495
Filename
257495
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