Title :
Fast pipelined multipliers for bit-serial complex numbers
Author :
Breveglieri, Luca ; Piuri, Vincenzo ; Sciuto, Donatella
Author_Institution :
Dept. of Electron., Politecnico di Milano, Italy
Abstract :
A novel approach is presented for complex numbers in full fractional two´s complement representation. A class of multipliers is discussed and evaluated: the authors consider in particular the computational time, the throughput, and the silicon area required by a VLSI implementation. High regularity and modularity are some of the most interesting features of the architecture
Keywords :
digital arithmetic; multiplying circuits; pipeline processing; VLSI implementation; bit-serial complex numbers; full fractional two´s complement representation; modularity; pipelined multipliers; regularity; Adders; Circuits; Clocks; Computer applications; Computer architecture; Hardware; Propagation delay; Silicon; Throughput; Very large scale integration;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257496
