Title :
High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique
Author :
Oishi, A. ; Fujii, O. ; Yokoyama, T. ; Ota, K. ; Sanuki, T. ; Inokuma, H. ; Eda, K. ; Idaka, T. ; Miyajima, H. ; Iwasa, S. ; Yamasaki, H. ; Oouchi, K. ; Matsuo, K. ; Nagano, H. ; Komoda, T. ; Okayama, Y. ; Matsumoto, T. ; Fukasaku, K. ; Shimizu, T. ; Miya
Author_Institution :
Semicond. Co., Toshiba Corp., Tokyo
Abstract :
High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced mobility enhancement is performed and it is confirmed that the new scheme such as eSiGe and stress liner techniques are suitable for 45nm technology CMOSFET. It is confirmed that the stress enhancement factors using multiple booster techniques remain valid, which proves that these techniques are scalable for future technology
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; carrier mobility; silicon compounds; stress effects; 45 nm; CMOSFET technology; SiGe; SiON; gate stack scaling; junction scaling; multiple booster techniques; poly-Si gate depletion; process-induced mobility enhancement; reversed-order junction formation; short channel effect; stress enhancement factors; stress-induced mobility enhancement technique; CMOS technology; CMOSFETs; Compressive stress; Large scale integration; MOSFET circuits; Nitrogen; Optimized production technology; Scalability; Space technology; Tensile stress;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609314
