DocumentCode :
3441730
Title :
Recursive bipartitioning of signal flow graphs for programmable video signal processors
Author :
Aarts, E.H.L. ; Essink, G. ; de Kock, E.A.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fYear :
1996
fDate :
11-14 Mar 1996
Firstpage :
460
Lastpage :
466
Abstract :
We consider the problem of partitioning video algorithms over an arbitrary network of high-performance video signal processors. The partitioning problem under consideration is very hard due to the many constraints that need to be satisfied. We present a solution strategy based on a recursive bipartitioning approach, which effectively handles the routing of the data flows through the network under time and resource constraints. The bipartitions are generated using a variable-depth search algorithm. We present results for industrially relevant video algorithms
Keywords :
circuit CAD; digital signal processing chips; integrated circuit design; real-time systems; signal flow graphs; video signal processing; DSP chips; SFG partitioning; programmable video signal processors; recursive bipartitioning; resource constraints; signal flow graphs; solution strategy; time constraints; variable-depth search algorithm; video algorithms; Digital signal processing; Flow graphs; Partitioning algorithms; Processor scheduling; Routing; Signal mapping; Signal processing; Signal processing algorithms; Time factors; Video signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7424-5
Type :
conf
DOI :
10.1109/EDTC.1996.494341
Filename :
494341
Link To Document :
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