DocumentCode :
3441818
Title :
A fast optimal robust path delay fault testable adder
Author :
Becker, B. ; Drechsler, Rolf ; Krieger, Rolf ; Reddy, Sudhakar M.
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
fYear :
1996
fDate :
11-14 Mar 1996
Firstpage :
491
Lastpage :
498
Abstract :
In this paper we explore the test complexity of the adder function with respect to the robust path delay fault model. A lower bound of ω(n2) for the cardinality of a complete test set for a combinational n-bit adder is proven. This result is valid for any adder design known until now. In addition we present a fast O(√n)-time adder that is fully robust path delay fault testable with a test set of size Θ(n2)
Keywords :
adders; delays; digital arithmetic; fault diagnosis; logic testing; cardinality; combinational n-bit adder; fast optimal adder; lower bound; robust path adder; robust path delay fault model; test complexity; testable adder; Added delay; Adders; Circuit faults; Circuit testing; Cities and towns; Computer science; Manufacturing processes; Robustness; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7424-5
Type :
conf
DOI :
10.1109/EDTC.1996.494346
Filename :
494346
Link To Document :
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