A memory-based architecture for MPEG2 System protocol LSIs

Author

Inamori, Minoru ; Naganuma, Jiro ; Wakabayashi, Haruo ; Endo, Makoto

Author_Institution

NTT LSI Labs., Atsugi, Japan

fYear

1996

fDate

11-14 Mar 1996

Firstpage

500

Lastpage

507

Abstract

This paper proposes a memory-based architecture implementing the MPEG2 System protocol LSIs, and demonstrates its flexibility and performance. The memory-based architecture implements the full functionality of the MPEG2 System protocol for both multiplexing and de-multiplexing MPEG2-encoded streams. It consists of a core CPU, memories, and dedicated application-specific hardware. It is designed and optimized by hardware/software co-design techniques. The LSIs provide sufficient performance and flexibility for real-time applications of the MPEG2 System protocol

Keywords

audio coding; codecs; data compression; demultiplexing equipment; digital signal processing chips; large scale integration; memory architecture; multiplexing equipment; protocols; real-time systems; video coding; MPEG2 system protocol LSI; MPEG2-encoded streams; core CPU; dedicated application-specific hardware; demultiplexing; hardware/software codesign techniques; memory-based architecture; multiplexing; real-time applications; Code standards; Computer architecture; Decoding; Hardware; Large scale integration; Memory architecture; Protocols; Standards development; Streaming media; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494347

Filename

494347