A VLSI implementation of a novel bit-serial butterfly processor for FFT

A processing element (PE) that performs butterfly operations is described. The PE is completely bit-serial and computes the butterfly operation in 3(n+1) clock cycles (ck) where (n+1) is the word length. Operands have fixed point sign magnitude format. Hardware solutions adopted allow the computation in pipelined mode in ( n+1) ck. Floating point format can be adopted; the computation delay becomes 12(n+1) ck, assuming 2(n+1) the word length. CMOS implementation is discussed with maximum clock frequency over 40 MHz