Title :
A VLSI implementation of a novel bit-serial butterfly processor for FFT
Author :
Di Lecce, V. ; Di Sciascio, E.
Author_Institution :
Dipartimento di Elettrotecnica ed Elettronica, Bari Univ., Italy
Abstract :
A processing element (PE) that performs butterfly operations is described. The PE is completely bit-serial and computes the butterfly operation in 3(n+1) clock cycles (ck) where (n+1) is the word length. Operands have fixed point sign magnitude format. Hardware solutions adopted allow the computation in pipelined mode in ( n+1) ck. Floating point format can be adopted; the computation delay becomes 12(n+1) ck, assuming 2(n+1) the word length. CMOS implementation is discussed with maximum clock frequency over 40 MHz
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; 40 MHz; CMOS implementation; FFT; VLSI implementation; bit-serial butterfly processor; computation delay; fixed point sign magnitude format; Biomedical computing; Clocks; Digital signal processing; Discrete Fourier transforms; Hardware; Parallel architectures; Signal processing; Throughput; Timing; Very large scale integration;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257507
