Design of analogue synapse circuits using non-volatile a-Si:H memory devices

Analogue hardware implementations of neural networks have hitherto been hampered by the lack of a straightforward analogue memory capability. The synaptic weights which are developed by the network learning process must be stored (preferably at each synapse site) in order that a network can adequately perform any recall or classification tasks. Ideally, the storage mechanism should be compact, non-volatile, easily reprogrammable, and simple to implement. Techniques which have been used to date include resistors (these are not generally reprogrammable, and suffer from being large and difficult to fabricate with any accuracy), dynamic capacitive storage (this is compact, reprogrammable and simple, but implies an increase in system complexity, arising from off-chip refresh circuitry), EEPROM (“floating gate”) memory (which is compact, reprogrammable, and non-volatile, but cannot be reprogrammed in situ), and local digital storage (which is non-volatile, easily programmable and simple, but is very costly in “real estate” terms). In this paper, we demonstrate that novel amorphous silicon memory devices can be incorporated into standard CMOS synapse circuits, to provide an analogue weight storage mechanism which is compact, non-volatile, easily reprogrammable, and simple to implement