CMOS layout and bias optimization for RF IC design applications

Author

Cheon Soo Kim ; Hyun Kyu Yu ; Hanjin Cho ; Seonghearn Lee ; Kee Soo Nam

Author_Institution

Compound Semicond. Dept., Electron. & Telecommun. Res. Inst., Daejeon, South Korea

Volume

2

fYear

1997

fDate

8-13 June 1997

Firstpage

945

Abstract

High frequency and low noise performance of 0.8 /spl mu/m polysilicon gate CMOS device has been analyzed intensively with the various multi-finger polysilicon gate layout and bias to find the optimal condition. From the analysis, the optimal width of unit gate finger and bias condition have been found to maximize f/sub max/ and minimize F/sub min/. At the conditions, F/sub min/, gain and noise resistance characteristics of large width transistors are also analyzed.

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF measurement; circuit optimisation; elemental semiconductors; field effect MMIC; integrated circuit design; integrated circuit measurement; integrated circuit noise; microwave measurement; silicon; 0.8 micron; CMOS layout; IC design; bias optimization; large width transistors; low noise performance; multi-finger polysilicon gate; noise resistance characteristics; optimal width; Application specific integrated circuits; CMOS integrated circuits; CMOS technology; Design optimization; Fingers; Frequency measurement; Integrated circuit layout; MOSFETs; Radio frequency; Radiofrequency integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 1997., IEEE MTT-S International

Conference_Location

Denver, CO, USA

ISSN

0149-645X

Print_ISBN

0-7803-3814-6

Type

conf

DOI

10.1109/MWSYM.1997.602956

Filename

602956