The POTATO chip architecture: a study in tradeoffs for signal processing chip design

Author

Sharma, B. ; Jain, R. ; Breuer, M.A. ; Parker, A.C. ; Raghavendra, C. ; Tseng, C.Y.

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

508

Lastpage

513

Abstract

The authors describe an example signal-processing design which illustrates partitioning, performance, cost, and fault-tolerance tradeoffs. They focus on high-performance multiplication using the power-of-two number representation as implemented in the POTATO (power of two arithmetic time-optimized) chip architecture. The implementation is compared to more conventional designs, and performance estimates are given. It is concluded that the design compares favourably to more conventional implementations

Keywords

computer architecture; digital arithmetic; digital signal processing chips; fault tolerant computing; performance evaluation; POTATO chip architecture; fault-tolerance tradeoffs; high-performance multiplication; performance estimates; power of two arithmetic time-optimized; power-of-two number representation; signal processing chip design; Algorithm design and analysis; Arithmetic; Chip scale packaging; Computer architecture; Fault tolerant systems; Hardware; Parallel architectures; Signal design; Signal processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25752

Filename

25752