ETS-A: a new electrothermal simulator for CMOS VLSI circuits

In this paper, we present a method for finding the CMOS VLSI chip temperature profile and the corresponding circuit performance by using a new electrothermal simulator, ETS-A. We use a sequence of procedures: layout extraction with x-y coordinates for individual transistors, fast timing-based power calculation, analytical thermal simulation using integral transform, followed by the electrothermal iterations until convergence. ETS-A takes advantage of the fast timing simulator while preserving the accuracy with use of temperature-dependent region-wise quadratic (RWQ) MOS transistor modeling techniques. The novel mixed 3-D & 1-D thermal simulator implemented in ETS-A efficiently takes into account the chip packaging and the thermal boundary conditions (BCs), which were often ignored in typical thermal simulations. With ETS-A, on-chip temperature profile can be calculated and further applied to guide the temperature-driven module placement as well as chip packaging designs