CMOS design of two winner-take-all circuits using pulse duty cycle synaptic weighting

In this paper the pulse coded Neural Processing Element (NPE) is used to realize two Winner-Take-All (WTA) systems which use an Hebbian type learning rule for setting the synaptic weights. The two systems, temporal and maximum-level, use the same circuit with a small connection change. In the NPE the average pulse duty cycle modulation technique is used to achieve pulse coded weighting for an artificial neuron. The average pulse duty cycle serves as an information mechanism to determine the weight multiplication. SPICE simulations check the theory with a CMOS prototype chip designed and fabricated through MOSIS. Measurements on the chip compared with simulation results verify the operation of the WTA circuitry