Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design

Author

Rullán, M. ; Ferrer, C. ; Oliver, J. ; Mateo, D. ; Rubio, A.

Author_Institution

CNM, Univ. Autonoma de Barcelona, Spain

fYear

1996

fDate

11-14 Mar 1996

Firstpage

584

Lastpage

588

Abstract

Difference between ISSQ and IDDQ testing strategies is presented, discussing the dependency of area overhead and sensing speed on the technology. The current sensor implementation style suitable for cell-based design methodology or semi-custom design style is proposed Experimental results for each strategy are discussed. Finally, different types of partitioning strategies are showed, taken into account the parallelism of the gates

Keywords

CMOS logic circuits; application specific integrated circuits; automatic testing; cellular arrays; fault diagnosis; integrated circuit testing; logic partitioning; logic testing; CMOS cell-based design; IDDQ testing; ISSQ testing; area overhead; circuit partitioning; parallelism; partitioning strategies; semi-custom design style; sensing speed; testing strategies; CMOS technology; Circuit faults; Circuit testing; Design methodology; Integrated circuit interconnections; Libraries; Logic testing; Monitoring; Rails; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494360

Filename

494360

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3442060