A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

Author

Minami, Yoshihiro ; Shino, Tomoaki ; Sakamoto, Atsushi ; Higashi, Tomoki ; Kusunoki, Naoki ; Fujita, Katsuyuki ; Hatsuda, Kosuke ; Ohsawa, Takashi ; Aoki, Nobutoshi ; Tanimoto, Hiroyoshi ; Morikado, Mutsuo ; Nakajima, Hiroomi ; Inoh, Kazumi ; Hamamoto, Ta

Author_Institution

SoC Res. & Dev. Center, Toshiba Corp., Yokohama

fYear

2005

fDate

5-5 Dec. 2005

Firstpage

307

Lastpage

310

Abstract

A 128Mb SOI DRAM with FBC (floating body cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i) In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii) Cu wiring has been used for bit line (BL) and source line (SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS technology

Keywords

CMOS memory circuits; DRAM chips; copper; logic design; memory architecture; silicon-on-insulator; 128 Mbit; 90 nm; CMOS technology; Cu; SOI DRAM; array device; bit line; floating body cell; peripheral circuit; source line; CMOS process; CMOS technology; Circuits; Design optimization; Immune system; Large scale integration; Random access memory; Research and development; Switches; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-9268-X

Type

conf

DOI

10.1109/IEDM.2005.1609336

Filename

1609336