Title :
Technology for sub-50nm DRAM and NAND flash manufacturing
Author_Institution :
Semicond. R&D Div., Samsung Electron. Co. Ltd., Kyunggi-Do
Abstract :
This paper discusses whether memory technologies can continue advances beyond sub-50nm node especially for DRAM and NAND flash memories. First, the barriers to shrink technology are addressed for DRAM and NAND flash memories, depending on their inherent operation principles. Then, details of technology solutions are introduced and its manufacturability is examined. Beyond 30nm node, It is expected that 3-dimensional transistor scheme is needed for both logic and memory array in addition to the development of new materials and structural technologies
Keywords :
DRAM chips; NAND circuits; flash memories; nanoelectronics; 3D transistor scheme; 50 nm; DRAM; NAND flash memories; shrink technology; Capacitance; High K dielectric materials; High-K gate dielectrics; Leakage current; Logic arrays; MIM capacitors; Manufacturing processes; Mass production; Random access memory; Transistors;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609340
