DocumentCode :
3442210
Title :
Challenges for the DRAM cell scaling to 40nm
Author :
Mueller, W. ; Aichmayr, G. ; Bergner, W. ; Erben, E. ; Hecht, T. ; Kapteyn, C. ; Kersch, A. ; Kudelka, S. ; Lau, F. ; Luetzen, J. ; Orth, A. ; Nuetzel, J. ; Schloesser, T. ; Scholz, A. ; Schroeder, U. ; Sieck, A. ; Spitzer, A. ; Strasser, M. ; Wang, P.-F.
Author_Institution :
Infineon Technol., Dresden
fYear :
2005
fDate :
5-5 Dec. 2005
Lastpage :
339
Abstract :
This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures
Keywords :
DRAM chips; capacitors; DRAM cell scaling; DRAM materials; capacitor structures; cell transistor structures; Capacitance measurement; Capacitors; High K dielectric materials; High-K gate dielectrics; Parasitic capacitance; Random access memory; Temperature; Timing; Tin; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
Type :
conf
DOI :
10.1109/IEDM.2005.1609344
Filename :
1609344
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3442210
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