DocumentCode
3442351
Title
Realistic fault extraction for boards
Author
Sousa, J.T. ; Shen, T. ; Cheung, P.Y.K.
Author_Institution
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
fYear
1996
fDate
11-14 Mar 1996
Firstpage
612
Abstract
Extraction of realistic faults in boards can improve test synthesis, fault coverage, diagnostic resolution and repair time. A methodology and a tool for board inductive fault analysis is proposed. Results on real examples prove the efficiency of the approach
Keywords
automatic testing; fault diagnosis; fault location; printed circuit testing; PCB testing; board testing; diagnostic resolution; fault coverage; inductive fault analysis; realistic fault extraction; test synthesis; Educational institutions; Electronic equipment testing; Fault diagnosis; Pins; Sun; System testing; Workstations; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location
Paris
ISSN
1066-1409
Print_ISBN
0-8186-7424-5
Type
conf
DOI
10.1109/EDTC.1996.494376
Filename
494376
Link To Document