Applying behavioural level test generation to high-level design validation

Summary form only given. The methods for verifying an implementation with respect to the specified behavioural VHDL description are not sufficiently developed yet. Therefore the correct behaviour of the implementation has to be validated by simulation. Since it is impossible to simulate the implementation completely, suitable simulation patterns have to be selected for executing statements, operations, functions, etc. of the implementation. In practice many designer use simulation patterns that reflect the adequate behaviour of the specification. But often these patterns do not fulfil completeness criteria and some functions may remain untested. In order to achieve a systematic determination and selection of the simulation patterns it is suggested that test generation methods be applied at the behavioural level. Hence the authors describe the test generation approach GESTE, which is characterized by the following: the generation of symbolic tests by solving a system of equations and inequalities; internal model comprising control and data flow; and application of structure-oriented and software testing methods