A highly parallel processor with an instruction set including relational algebra

Author

Faudemay, Pascal ; Etiemble, Daniel ; Bechennec, Jean-Luc

Author_Institution

MASI Lab., Paris Univ., France

fYear

1988

fDate

3-5 Oct 1988

Firstpage

537

Lastpage

538

Abstract

The authors present RAPID a highly parallel processor which includes an extended relational algebra and text retrieval capacities in its instruction set. RAPID operates in parallel with the transfer of relevant data on the host machine bus, in a null apparent time. It is implemented with several copies of a specialized component using RISC (reduced-instruction-set-computer)-like technology, though its instructions are very high-level ones. It fully uses the resources of HCMOS3 technology and of full-custom design. A first version of the processor is presently being implemented

Keywords

CMOS integrated circuits; instruction sets; parallel architectures; parallel machines; reduced instruction set computing; relational databases; HCMOS3 technology; RAPID; RISC; full-custom design; instruction set; parallel processor; reduced-instruction-set-computer; relational algebra; text retrieval; Aggregates; Algebra; Broadcasting; Data models; Database machines; Parallel machines; Protocols; Relational databases; Sorting; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25757

Filename

25757