Concatenating Packets in Variable-Length Input-Queued Packet Switches with Cell-Based and Packet-Based Scheduling

Internet data is transmitted in variable-size packets to provide flexibility for different applications. There has been a growing interest in developing the design of Internet routers based variable-length packets to improve performance and reduce the amount of re-assembly memory. However, most of variable-length designs follow a time-slotted approach, which make them similar to routers that switch fixed-length packets. The use of slotted timing makes padding necessary when packet sizes are not proportional to the time-slot length. In this paper, we investigate the impact of concatenating packets to reduce the amount of padding in variable-length packet switches. This approach increases the utilization of interconnection bandwidth and overall throughput performance. Performance evaluation in an input-queued packet switch using packet concatenation is presented.