Title :
Simulated annealing on a multiprocessor
Author :
Chamberlain, Roger D. ; Edelman, M.N. ; Franklin, Mark A. ; Witte, Ellen E.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Washington Univ., St. Louis, MO, USA
Abstract :
The authors present a method for parallelizing the simulated annealing algorithm by mapping the algorithm onto a dynamically structured tree of processors. The resulting parallel simulated annealing algorithm is discussed and its performance evaluated using simulation techniques. An important property of the parallel algorithm is that it maintains the same move decision sequence as the serial simulated annealing algorithm, thus avoiding problems associated with move conflicts and erroneous move acceptance/rejection decisions which have been associated with other parallel simulated annealing algorithm proposals. The parallel algorithm presented achieves speedups between log2N and (N+log2N)/2 where N is the number of processors in the parallel processor. Experimental results are presented on three versions of the basic method: the static, dynamic balanced, and dynamic unbalanced parallel-simulated-annealing algorithms
Keywords :
computational complexity; optimisation; parallel algorithms; dynamic balanced algorithm; dynamic unbalanced algorithm; move decision sequence; multiprocessor; parallel algorithm; simulated annealing algorithm; static algorithm; Combinatorial mathematics; Computational modeling; Computer simulation; Concurrent computing; Design automation; Heuristic algorithms; Parallel algorithms; Predictive models; Proposals; Simulated annealing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25758