Title :
Performance evaluation of a RISC neuro-processor for neural networks
Author :
Kumar, Suthikshn ; Forward, Kevin ; Palaniswami, M.
Author_Institution :
Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
Abstract :
In this paper design details of a RISC neuro-processor are presented. Neural network applications of Hopfield networks, self-organizing feature maps and multilayer feedforward networks (MFNN) are used as benchmarks for performance evaluation of the neuro-processor. Extensive simulations have been carried out to study the cost performance issues of neuro-processor hardware architecture. A quantitative approach is employed in designing cost-effective implementation of the neuro-processor. Special instructions have been provided in the neuro-processor instruction-set to improve the speed of both implementation and execution of neural networks. Instruction-set usage measurements have been used to study the effectiveness of the instruction-set design. Branch behaviour statistics have been studied in order to adopt good branch prediction strategies
Keywords :
Hopfield neural nets; feedforward neural nets; neural net architecture; performance evaluation; reduced instruction set computing; self-organising feature maps; Hopfield networks; RISC neuro-processor; benchmarks; branch behaviour statistics; branch prediction strategies; cost performance; instruction-set; instruction-set usage measurements; multilayer feedforward networks; neural networks; performance evaluation; self-organizing feature maps; Artificial neural networks; Computer architecture; Design engineering; Digital signal processing; Hopfield neural networks; Multi-layer neural network; Neural network hardware; Neural networks; Reduced instruction set computing; Statistics;
Conference_Titel :
High Performance Computing, 1996. Proceedings. 3rd International Conference on
Conference_Location :
Trivandrum
Print_ISBN :
0-8186-7557-8
DOI :
10.1109/HIPC.1996.565846
