DocumentCode :
3443320
Title :
Some limitations to speed-independence in asynchronous circuits
Author :
Bush, Martin E. ; Josephs, Mark B.
Author_Institution :
Centre for Concurrent Syst., South Bank Polytech., London, UK
fYear :
1996
fDate :
18-21 Mar 1996
Firstpage :
104
Lastpage :
111
Abstract :
Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs´ Receptive Process Theory
Keywords :
asynchronous circuits; formal specification; logic design; Josephs´ Receptive Process Theory; asynchronous circuits; commutativity; formal analysis; inertia; persistence; speed-independence; Asynchronous circuits; Circuit synthesis; Delay; Interference; Logic circuits; Logic design; Logic gates; Pulse circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on
Conference_Location :
Fukushima
Print_ISBN :
0-8186-7298-6
Type :
conf
DOI :
10.1109/ASYNC.1996.494442
Filename :
494442
Link To Document :
بازگشت