Title :
A new charge-trapping technique to extract SILC-trap time constants in SiO/sub 2/
Author :
Ielmini, D. ; Spinelli, A.S. ; Lacaita, A.L. ; Chiavarone, L. ; Visconti, A.
Author_Institution :
Dipt. di Elettronica e Informazione, Politecnico di Milano
Abstract :
A new experimental technique for investigating the trapping-detrapping time constants for electrons at stress-induced defects in the silicon oxide is presented. The new technique is based on the gate-stress measurement for flash memories, with the application of a pulsed gate voltage. Data for 512 Kbit NOR-flash arrays are presented, and analyzed by analytical and Monte Carlo models for the trap-assisted tunneling mechanism under pulsed conditions. Comparison between experimental data and calculations for selected cells allows for an estimation of the energy and spatial depth of the oxide traps
Keywords :
Monte Carlo methods; NOR circuits; electron traps; elemental semiconductors; flash memories; integrated circuit modelling; integrated circuit reliability; integrated memory circuits; leakage currents; silicon compounds; stress effects; 512 kbit; Monte Carlo models; NOR-flash arrays; SILC-trap time constants; SiO2; charge-trapping technique; flash memories; gate-stress measurement; stress-induced defects; trap-assisted tunneling mechanism; trapping-detrapping time constants; Character generation; Electron emission; Electron traps; Flash memory; Monte Carlo methods; Nonvolatile memory; Pulse measurements; Pulse modulation; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609403
