A dual-mode digital DC-DC converter based on distributed arithmetic

This paper presents the design of an area-efficient and reconfigurable dual-mode (PWM/PFM) digital DC-DC controller based on distributed arithmetic. The proposed digital DC-DC controller is realized in current-mode topology to achieve better line regulation. It also features a memory-reuse concept for further area reduction and dual-mode (PFM/PWM) reconfigurability. This design is verified with measurements on a Virtex-4 FPGA board. Simulation results show that the number of FPGA slices and Look-Up Tables is reduced by 57% and 45% respectively. Power consumption based on implementation is reduced by 57.6% to 22mW. With a switching frequency of 390kHz, the measured tracking speed of the converter for a maximum load current step (0 to 500mA) is 62.5μs/V.