DocumentCode :
3443544
Title :
Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFETs
Author :
Chan, C.T. ; Tang, C.J. ; Tahui Wang ; Wang, H.C.-H. ; Tang, D.D.
Author_Institution :
Dept. of Electron. Eng., National Chiao Tung Univ.
fYear :
2005
fDate :
5-5 Dec. 2005
Firstpage :
563
Lastpage :
566
Abstract :
Positive bias and temperature (PBTI) stress induced drain current degradation in HfSiON gate dielectric nMOSFETs is investigated by using a transient measurement technique. The degradation exhibits two stages, featuring different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation. Process effect on high-k trap growth is evaluated
Keywords :
MOSFET; dielectric materials; hafnium compounds; high-k dielectric thin films; semiconductor device breakdown; silicon compounds; stress effects; thermal stresses; HfSiON; PBTI stress induced drain current degradation; degradation rate; dielectric nMOSFET; high-k dielectric traps; high-k trap growth; positive bias and temperature stress induced drain current degradation; stress temperature dependence; transient measurement technique; two-stage drain current degradation; Acceleration; Current measurement; Degradation; High K dielectric materials; High-K gate dielectrics; MOSFETs; Measurement techniques; Stress measurement; Temperature dependence; Time measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
Type :
conf
DOI :
10.1109/IEDM.2005.1609408
Filename :
1609408
Link To Document :
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